src-vorago-common merge requestshttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests2020-12-15T15:10:59Zhttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/1Added scripts to upload binaries2020-12-15T15:10:59ZRobin MuellerAdded scripts to upload binarieshttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/2Hotfix of Rebboard2020-12-15T15:09:40ZLorenz MaurerHotfix of RebboardThe interrupt destination from VORAGO was flawed. Fixes #3The interrupt destination from VORAGO was flawed. Fixes #3https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/3Fix Gpio-Driver2021-01-26T15:51:59ZLorenz MaurerFix Gpio-DriverDefinition of Gpio_Port_B_12 was missingDefinition of Gpio_Port_B_12 was missinghttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/4Minor Updates2021-01-26T15:53:57ZRobin MuellerMinor UpdatesSome formatting stuff, TODO for possibly buggy line that I can not test.Some formatting stuff, TODO for possibly buggy line that I can not test.https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/5Fix SPI Send and Transmit2021-03-04T10:44:17ZErik ZeiskeFix SPI Send and TransmitSend:
The library was not waiting till the transmit is complete resulting in a
second call to SPI_Send clearing the previous call.
Transmit:
This call was going further and disabled the SPI interface before
anything was able to transmit...Send:
The library was not waiting till the transmit is complete resulting in a
second call to SPI_Send clearing the previous call.
Transmit:
This call was going further and disabled the SPI interface before
anything was able to transmit. This was due to the fact that the num--;
was placed wrong and after putting everything into the transmit queue
there was no wait to retrieve everything from the receive queue.
As the code for the poll timeout was weird and the default timeout was
not set anyway. We could think about rewriting this code later though
(but I think it should only be necessary if we are an SPI client)https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/6UART driver updates2021-04-14T18:09:37ZRobin MuellerUART driver updatesRenamed `UartTask` to `UartReaderTask` to make the intent of the class more clear. Also added docs.
These driver still need to be updated to handle USLP (Unified Space Data Link) protocol packets with fixed size, I tested them with newli...Renamed `UartTask` to `UartReaderTask` to make the intent of the class more clear. Also added docs.
These driver still need to be updated to handle USLP (Unified Space Data Link) protocol packets with fixed size, I tested them with newline separated strings of variable size and an Arduino Nano Every. So simplifications and improvements here are definitely possible.https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/7Vorago UART Bugfixes and functions to disable and enable interrupts2021-04-27T11:24:47ZRobin MuellerVorago UART Bugfixes and functions to disable and enable interrupts- Add functions to enable or disable interrupts. Important for critical sections when there is no RTOS present
- Some important fixes in the Vorago UART interrupt handler and some minor tweaks
- The interrupt handler was not able to proc...- Add functions to enable or disable interrupts. Important for critical sections when there is no RTOS present
- Some important fixes in the Vorago UART interrupt handler and some minor tweaks
- The interrupt handler was not able to process a simple string "Hello World!\n\r" received each 5 seconds. This was fixed by the following chages:
1. RX status register is re-read after reading data from the FIFO because it might have changed (e.g. timeout has occured)
2. If a timeout has occured, the remaining data in the FIFO is read
- I tested these changes with the aforementioned string and a larger string which exceeds the FIFO size (about 40 bytes size) and I was able to receive those properly
- Adds option to disable or enable the periodic printout from the test task, which can be set from configuration file with `VOR_TEST_TASK_PERIODIC_OUTPUT`
- The issue might also be related to the use of the RS485 transceiver. I have not tested communication without the transceiver (at least thats a long time ago). But communication via RS485 is our use-case anywayhttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/8Update Common2021-08-13T07:48:56ZRobin MuellerUpdate Common- A lot of form changes because the Vorago libs tend to have horrible indentation
- Some flash programming algorithms set up
- Bootloader: Added command to set CRC16
- It is recommended to disbale showing of whitespace changes- A lot of form changes because the Vorago libs tend to have horrible indentation
- Some flash programming algorithms set up
- Bootloader: Added command to set CRC16
- It is recommended to disbale showing of whitespace changesv1.2.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/9Introduce CMake2021-08-13T07:49:20ZRobin MuellerIntroduce CMake- Switched build system to CMake and updated documentation accordingly
- Merge !8 first- Switched build system to CMake and updated documentation accordingly
- Merge !8 firstv1.2.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/10Self-Flasher Application2021-08-13T07:50:21ZRobin MuellerSelf-Flasher Application- Added self-flasher features which allow self-flashing a RAM image into NVM. This works via configuration options
and instructions will follow in a separate PR
- Improved architecture of bootloader- Added self-flasher features which allow self-flashing a RAM image into NVM. This works via configuration options
and instructions will follow in a separate PR
- Improved architecture of bootloaderv1.2.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/11added version tags for common submodule2021-08-13T07:50:07ZRobin Muelleradded version tags for common submoduleImportant for traceabilityImportant for traceabilityv1.2.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/12v1.2.02021-08-13T07:51:32ZRobin Muellerv1.2.0- A lot of form changes because the Vorago libs tend to have horrible indentation
- Some flash programming algorithms set up
- Bootloader: Added command to set CRC16
- Switched build system to CMake and updated documentation accordingly
...- A lot of form changes because the Vorago libs tend to have horrible indentation
- Some flash programming algorithms set up
- Bootloader: Added command to set CRC16
- Switched build system to CMake and updated documentation accordingly
- Added self-flasher features which allow self-flashing a RAM image into NVM. This works via configuration options
and instructions will follow in a separate PR
- Improved architecture of bootloaderv1.2.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/14Update Vorago Common2021-09-24T08:34:30ZRobin MuellerUpdate Vorago Common- Several improvements for existing modules- Several improvements for existing modulesv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/15ADC Update2021-10-19T10:04:16ZRobin MuellerADC Update- Better logger printouts
- ADC updates: Renamed because code can also be used for other MAX ADC devices
- New uSec delay function in `Clock` module
- Top view of REB1 board with SPI pinouts marked- Better logger printouts
- ADC updates: Renamed because code can also be used for other MAX ADC devices
- New uSec delay function in `Clock` module
- Top view of REB1 board with SPI pinouts markedv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/16Updated UART components2021-10-19T18:29:00ZRobin MuellerUpdated UART components- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation. It worked in t...- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation. It worked in the first tests
- `UartTestTask` moved to Vorago Commonv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/17Refactoring driver assignment and UART Test Task fixes2021-10-20T10:04:28ZRobin MuellerRefactoring driver assignment and UART Test Task fixes- UART pin assignment was hardcoded but a lot more combinations are possible
- The pin assigment is now passed in form of a user callback instead
- Bugfixes in UART Test Task callback- UART pin assignment was hardcoded but a lot more combinations are possible
- The pin assigment is now passed in form of a user callback instead
- Bugfixes in UART Test Task callbackv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/18uart handler fixes2021-10-20T10:36:59ZRobin Muelleruart handler fixes- Cleaned up and improved UART handler, improved code documentation as well- Cleaned up and improved UART handler, improved code documentation as wellv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/19Update to v1.3.02021-10-20T10:42:32ZRobin MuellerUpdate to v1.3.0- Updates structure of common folder
- Better logger printouts
- New SPI Handler helper class
- New ADC class for Max127xx devices
- Top view of REB1 board with SPI pinouts marked
- Cleaned up UART components, there is one `UartHandler` ...- Updates structure of common folder
- Better logger printouts
- New SPI Handler helper class
- New ADC class for Max127xx devices
- Top view of REB1 board with SPI pinouts marked
- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation, worked in tests so far
- `UartTestTask` moved to Vorago Commonv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/20v1.3.12021-10-20T10:46:48ZRobin Muellerv1.3.1 - Bumped release - Bumped releasehttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/21Update to 1.4.02021-11-27T16:48:33ZRobin MuellerUpdate to 1.4.0- Add SVD file, useful for debugging
- Fixes for ADC code
- Arrayprinter format updates- Add SVD file, useful for debugging
- Fixes for ADC code
- Arrayprinter format updatesv1.4.0