src-vorago-common merge requestshttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests2021-10-20T10:42:32Zhttps://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/19Update to v1.3.02021-10-20T10:42:32ZRobin MuellerUpdate to v1.3.0- Updates structure of common folder
- Better logger printouts
- New SPI Handler helper class
- New ADC class for Max127xx devices
- Top view of REB1 board with SPI pinouts marked
- Cleaned up UART components, there is one `UartHandler` ...- Updates structure of common folder
- Better logger printouts
- New SPI Handler helper class
- New ADC class for Max127xx devices
- Top view of REB1 board with SPI pinouts marked
- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation, worked in tests so far
- `UartTestTask` moved to Vorago Commonv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/18uart handler fixes2021-10-20T10:36:59ZRobin Muelleruart handler fixes- Cleaned up and improved UART handler, improved code documentation as well- Cleaned up and improved UART handler, improved code documentation as wellv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/17Refactoring driver assignment and UART Test Task fixes2021-10-20T10:04:28ZRobin MuellerRefactoring driver assignment and UART Test Task fixes- UART pin assignment was hardcoded but a lot more combinations are possible
- The pin assigment is now passed in form of a user callback instead
- Bugfixes in UART Test Task callback- UART pin assignment was hardcoded but a lot more combinations are possible
- The pin assigment is now passed in form of a user callback instead
- Bugfixes in UART Test Task callbackv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/16Updated UART components2021-10-19T18:29:00ZRobin MuellerUpdated UART components- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation. It worked in t...- Cleaned up UART components, there is one `UartHandler` now which is now more configurable
- Made parts of Vorago UART driver const correct
- Changed UART interrupt handler of UART driver so support full-duplex operation. It worked in the first tests
- `UartTestTask` moved to Vorago Commonv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/15ADC Update2021-10-19T10:04:16ZRobin MuellerADC Update- Better logger printouts
- ADC updates: Renamed because code can also be used for other MAX ADC devices
- New uSec delay function in `Clock` module
- Top view of REB1 board with SPI pinouts marked- Better logger printouts
- ADC updates: Renamed because code can also be used for other MAX ADC devices
- New uSec delay function in `Clock` module
- Top view of REB1 board with SPI pinouts markedv1.3.0https://git.ksat-stuttgart.de/source/src-vorago-common/-/merge_requests/14Update Vorago Common2021-09-24T08:34:30ZRobin MuellerUpdate Vorago Common- Several improvements for existing modules- Several improvements for existing modulesv1.3.0